1. Field of the Invention
The present invention relates to a graphics drawing image processing apparatus and more particularly, relates to technology for accessing a built-in memory and external memory when combining a dynamic random access memory (DRAM) or other memory requiring refreshing and a logic circuit and further providing an external memory.
2. Description of the Related Art
Computer graphics are often used in a variety of computer aided design (CAD) system and amusement apparatuses. Especially, along with recent advances in image processing techniques, systems using three-dimensional computer graphics are becoming rapidly widespread.
In three-dimensional computer graphics, the color value of each pixel is calculated at the time of deciding the color of each corresponding pixel, and rendering is performed for writing the calculated value of the pixel to an address of a display buffer (frame buffer) corresponding to the pixel.
One of the rendering methods is polygon rendering. In this method, a three-dimensional model is expressed as a composite of triangular unit graphics (polygons). By drawing the polygons as units, the colors of the display screen are decided.
In polygon rendering, coordinates (x, y, z), color data (R, G, B), homogeneous coordinates (s, t) of texture data indicating a composite image pattern, and a value of the homogeneous term q for each vertex of the triangle in a physical coordinate system are input and processing is performed for interpolation of these values inside the triangle.
Here, looking at the homogeneous term q, the coordinates in a UV coordinate system of an actual texture buffer, namely, texture coordinate data (u, v), are comprised of the homogeneous coordinates (s, t) divided by the homogeneous term q to give “s/q” and “t/q”, which in turn are multiplied by texture sizes USIZE and VSIZE, respectively.
FIG. 12 is a view of the system configuration showing the basic concept of a three-dimensional computer graphics system.
In this three-dimensional computer graphics system, data for drawing graphics is supplied from a main memory 2 in a main processor 1 or from an input/output (I/O) interface circuit 3 for receiving graphics data from the outside via a main bus 4 to a rendering circuit 5 having a rendering processor 5a and a frame buffer memory 5b. 
In the rendering processor 5a, a frame buffer memory 5b for holding data for display and a texture memory 6 for holding texture data to be applied on the surface of a graphic element (for example, a triangle) to be drawn are connected.
Then, by the rendering processor 5a, processing for drawing the graphic element applied with the texture on its surface for every graphic element in the frame buffer memory 5b is performed.
The frame buffer memory 5b and the texture memory 6 are generally configured by a DRAM.
Then, in the system of FIG. 12, the frame buffer memory 5b and the texture memory 6 are configured as physically separated memory systems.
In a graphics drawing image processing apparatus, however, the memory is frequently accessed, such as for writing and reading image data to and from the memory and for reading for display of the image. Further, it becomes necessary to secure a wide bus width of the memory to obtain the full graphics drawing performance.
As a result, it has become physically impossible to arrange separately the graphics drawing image processing apparatus and memory due to the increase of the number of interconnections, so the DRAM and the logic circuit began to be provided on one chip.
Summarizing the problems to be solved by the invention, as mentioned above, in a graphics drawing image processing apparatus, it became easy to secure the bus width by arranging the memory inside the LSI.
However, it is necessary to make the built-in DRAM larger in capacity to improve the performance, but the enlargement of the capacity is difficult in actuality due to restrictions on the size of the chip.
In this case, the memory is frequently accessed for being rewritten from the outside due to the shortage of the memory capacity. This exerts a large influence upon the performance.
Also, reconnection of the external memory can be considered in order to achieve enlargement of the capacity, but simple expansion causes the disadvantage that the processing speed and the latency (reaction speed) become slow.